The present invention broadly relates to a method for manufacturing a semiconductor device having a laminated gate electrode.
As a gate electrode of a next-generation MOS transistor, expectation is placed on a tungsten polymetal structure containing tungsten and a polysilicon. A tungsten polymetal gate has extremely low resistance compared with a currently mainstream tungsten polycide gate (laminated structure of a polysilicon and a compound of tungsten and silicon), and has the following advantages in a semiconductor integrated circuit.
The first advantage is miniaturization. In the polycide structure, further miniaturization is difficult due to a problem with resistance values. This is because resistance values increase in inverse proportion to miniaturization in the same structure. By adopting the polymetal structure, it is possible to remove a barrier of the resistance value in miniaturization.
The second advantage is the capability of realizing a high-speed device. As determining factors of a device speed, gate resistance has relatively high ratio. By using a polymetal gate, the delay caused by the gate resistance is minimized.
The present inventors have succeeded in applying a tungsten polymetal gate technology to mass production. However, a fault (or a defect) of peeling-off occurs between a gate polysilicon and a gate oxide film. Generally, adhesion between the polysilicon and the oxide film is extremely high, and such a fault has rarely occurred in the past. In a portion where the peeling-off occurs, a threshold voltage of the MOS transistor is increased which prevents a circuit from operating normally.
As a result of investigation, it has been discovered that a main cause of the fault is a reduction in adhesion strength between the polysilicon and the oxide film caused by wet-hydrogen oxidation. Finally, a bird's beak stress triggered by the wet-hydrogen oxidation causes the peeling-off.